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In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore¡¯s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm, we seemingly pay very little attention to the humble interposer die that enables communication between these groundbreaking chiplets.

What Attendees Will Learn:

Synopsys tools can now improve the construction and signoff process for all styles of interposers. AMD has tested these tools and will present a comprehensive update on what we see as a step forward in interposer design. This flow is driven primarily within the Synopsys 3DIC Compiler platform, though other noteworthy tools and engines are employed at key stages to ensure a high standard of quality. The Synopsys webinar begins with a brief overview of the current interposer design flow, including pros and cons to the current approach and opportunities for new development. We¡¯ll then cover an end-to-end design flow that addresses these opportunities across the span of floorplanning, construction, extraction, and signoff. Finally, we¡¯ll wrap up with conclusions and future work.