91³Ô¹ÏÍø

Reducing Simulation Regression Turnaround Time with Dynamic Performance Optimization

No single step in the development of semiconductor devices is more sensitive to speed than functional simulation. A modern system-on-chip (SoC) design simulates billions of cycles of operation in the process of completing the verification plan and achieving coverage goals. To validate full system functionality, many of these simulations include running code on one or more embedded processors. Even pure hardware simulation tests are resource-intensive due to the size and complexity of the chip. Accordingly, anything that can be done to speed up simulation and reduce the turnaround time (TAT) for both individual tests and the overall regression suite is highly valuable.

?

Verification engineers are willing to devote a lot of effort to optimizing the testbench and tests to decrease runtime, even if only by a few percentage points. They take advantage of the cloud, compute grids, and multi-core machines to parallelize as much of the regressions as possible. They also spend significant effort in hand-tuning simulation parameters to minimize TAT. While all this work is considered worthwhile due to the payback, it consumes precious human resources during a critical phase of the project. This white paper presents an alternative approach that automates key aspects of optimizing simulation performance and reducing TAT. This is an essential step in SoC development, and it provides value for smaller chip projects as well.