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Ansys & Synopsys
Accelerating Multiphysics Design Success at the Intersection of Chips and Systems
Power, Thermal, and Reliability Signoff of Advanced SoCs, 2.5D and 3DIC
The design challenges that have emerged at 7nm and below, as well as with multi-die systems, can no longer be addressed as an afterthought at the very end of the design cycle. A range of novel physical effects, from thermal analysis to electromagnetic interference and advanced 3D layout capabilities, need to inform the design right from the prototyping stage. To deliver the industry¡¯s best EDA solution for these new challenges, and Synopsys have entered into a strategic alliance that builds on the companies¡¯ foundry-certified golden signoff technologies. of industry-leading power integrity, thermal, and reliability signoff products have been integrated with Synopsys' best-in-class Fusion Compiler? platform, 3DIC Compiler? platform and PrimeTime? signoff platform to provide customers golden signoff accuracy for chip, package, and system-level effects within the Synopsys design environment. This enables a faster, shift-left methodology with rapid design exploration, early weakness detection, in-design analysis, voltage-timing optimization, thermal-aware reliability, and final signoff from within the place-and-route environment.
Key Benefits
Unified Co-design & Analysis
Optimize PPA with the industry¡¯s first 2.5/3DIC solution
Superior PPA
Reduce peak and average power and improve design robustness
Environment-aware Chip Design
Architect chip and 3D package design for a range of operating environments
Areas of Collaboration
Address Your 3D Multi-Die, Multi-Node Implementation with Greater Confidence
solves the electrical and thermal coupling interactions of 2.5D/3DIC structures in full detail for up to a billion instances, concurrently. Synopsys¡¯ 3DIC Compiler platform provides a complete, end-to-end heterogeneous solution for efficient 2.5/3D multi-die design and full- system integration.? The result is a robust, integrated design development that accelerates 3D system-level convergence and optimizes power, performance and area (PPA/mm3) for heterogeneous design and 3D integration. Customers can address their 3D multi-die, multi-node implementation with greater confidence and bring products to market more quickly.
Accelerate Design Closure of Advanced Node Designs
Ansys and Synopsys collaborated to integrate RedHawk-SC with PrimeTime static timing analysis (STA) and Tweaker ECO, to provide designers signoff IR-aware STA analysis, and IR-ECO even at the late design stages to help improve PPA. The integrated flows enable Tweaker ECO fixes on targeted areas and includes very-fast interactive loops with RedHawk-SC to help deliver superior last-mile PPA closure, reduce peak and average power, and develop designs which are more robust across multiple scenarios. All these benefits improve the chip operational life cycle.
Design for a Range of Challenging Environments
Aerospace and defense customers have significant challenges to design low-SWaP, high-performance integrated circuits which work securely, safely and reliability in variety of challenging environments. Ansys¡¯ best-in-class multi-physics simulation capabilities complement the state-of-the-art design, verification, validation, and prototyping solutions offered by Synopsys. The combined Synopsys-Ansys flows enable aerospace and defense customers to do early analysis for 3DIC, digital design, and AMS design that identify the optimal architecture to operate in a specific environment or a range of environments.
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