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Effective Monitoring, Test, and Repair of Multi-Die Designs
Despite clear advantages, there are numerous new challenges that need to be addressed for successful multi-die realization.
This white paper focuses on the multi-die test challenges:
- Bare chiplet level (pre-bond)
- Probe, dedicated/functional pads for test
- Test, diagnosis, and repair
- Interconnects (mid/post-bond)
- Die-to-die test access
- Lane test, diagnosis, and repair
- Multi-die stack/package (post-bond)
- Die-to-die, stack/package test access
- Calibration, diagnosis, and repair
- Silicon debug and diagnosis
Find out how to overcome such challenges with Synopsys Test and Silicon Lifecycle Management 91³Ô¹ÏÍø. Synopsys provides comprehensive solutions for testing and repairing various types of die-to-die interfaces and lanes. The solutions test for and diagnose known-good stacks and know-good dies, support extensive BIST capabilities, and offer in-field interconnect monitoring for purposes such as predictive maintenance.