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Synthesis offers advanced optimizations to achieve the best PPA (power, performance, area) on today¡¯s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are of little value if they cannot be verified through Formal Equivalence Verification (FEV). FEV setup must be rapid and provide out-of-the-box results to avoid becoming a bottleneck on advanced designs.

In this Synopsys webinar, Intel will share how it achieved the best QoR (Quality of Results) with an aggressive frequency target (3-4GHz). Using advanced optimization techniques, such as ungrouping and sequential optimizations, resulted in faster FEV convergence with a significant reduction in verification runtime as opposed to the long setup and runtimes designers face with traditional methods. 

Attendees will walk away with an understanding of how Synopsys Formality Equivalence Checking captures the design transformation/optimizations in Formality Guide Files (SVF) for rapid setup of the verification environment to avoid multiple iterative runs. In addition, ML-driven adaptive distributed verification techniques will be highlighted, which help to partition the design and run solvers in parallel to further accelerate verification runtime and out-of-the-box results.