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Interfacing an SoC to the Real World with Data Converter IP
By Manuel Mota, Technical Marketing Manager for Data Converters, 91³Ô¹ÏÍø
Synopsys¡¯ DesignWare? Data Converter IP portfolio is typically considered to be a pure ¡°analog¡± IP function, but it can be argued that data converter IP is also ¡°interface¡± IP ¨C an interface to the real world. In effect, data converters are the foundation of the analog interfaces prevalent in most chips that interface with sensors and transducers (i.e., in microphones, speakers, camera sensors, accelerometers, thermometers, and pressure and touch sensors). In addition, data converters are also a critical element in wired and wireless communications transceivers where complex modulation schemes are used to overcome the limitations of harsh communication media: the air, power lines, and so on. Data converter IP can be described as another form of interface IP: ¡°analog interface IP.¡±
As illustrated in Figure 1, analog interfaces can be grouped into two categories: ones that adhere to formal standards (e.g., WiFi, LTE, CDMA, Bluetooth, G.hn, MoCA, and PLC) and others that do not follow a formal standard (e.g., most transducers: temperature, accelerometers, and pressure and sound sensors). Both categories have trends and requirements that are common to all of its applications. By analyzing these common requirements, generally required data converter IP characteristics emerge for each application space.
Figure 1: DesignWare Analog IP for Analog Interfaces
For example, modern communications protocols provide gigabit-per-second data rates to support the effective transfer of video/multimedia content. To support such high data rates, communications protocols resort to complex signal modulation schemes transmitted over communications channels as large as 80 MHz, as well as other techniques such as channel aggregation and complex multi-antenna architectures to improve the data rates and the immunity to the channel non idealities. From the baseband processor perspective, multi-antenna support translates into the support of multiple data streams simultaneously, each requiring a dedicated analog interface. High capacity protocols, such as WiFi 11ac, can implement up to eight antennas, and up to eight receive and eight transmit paths are used, each requiring a dedicated analog interface. A typical implementation of an LTE baseband in a handheld device supports two antennas, thus requiring two receive and two transmit paths.
Other applications, such as terrestrial, cable or satellite digital TV (DTV) reception, face similar challenges as the reception architecture evolves:
- High IF demodulation schemes simplify the design of an RFIC, and satellite reception uses broader band signaling, but both require higher sampling rates for the analog-to-digital converter (ADC)
- Implementing full band capture (FBC) architectures in TV tuners, where the complete spectrum is digitized for further digital processing with the help of an array of parallel ADCs, leads to the demand for area and power reduction. In addition, the extremely low form factor of flat panel displays leads to aggressive system integration which also requires power and area reduction.
Synopsys has addressed these application requirements by developing and evolving its DesignWare Data Converter IP, built on an advanced data converter architecture 1 that tackles all of these challenges with flexible data IP that can match the different requirements of most system implementations.
1. Higher sampling rate and performance
The DesignWare Analog-to-Digital Converter IP enables customers to follow the SoC integration paradigm and move the full functionality of the baseband processor into deep sub-micron processes, even for the most advanced protocols. As illustrated in Table 1, its ability to sample data up to 250 mega-samples per second (MSPS), while maintaining high linearity and low noise when processing broadband signals, makes it ideal for WiFi 11ac, LTE-A, PLC, and DTV reception applications.
Table 1: Typical resolution/sampling rate requirements for DesignWare ADC in different applications
Figure 2 illustrates DesignWare ADC IP performance while processing realistic signals. Linearity is demonstrated in terms of dual-tone inter-modulation distortion ratio (IMD) and of multi-tone power ratio (MTPR).
Figure 2: DesignWare ADC IP linearity: Dual and multi-tone characteristics (note: amplitude variation on MTPR measurement already present on input signal)
2. Area reduction
In deep sub-micron processes, silicon real estate is at a premium. To keep the area of the complete analog interface (analog front-end (AFE)) small even when the number of converters implemented is multiplied for multi-antenna support, the DesignWare ADC¡¯s area is minimized through digital calibration techniques that simplify the analog blocks and take full advantage of the smaller process geometry size.
Furthermore, the high sampling rate can be used in applications that require lower speeds--such as WiFi 11n, LTE, and some TV tuners. Using the optional built-in ¡°ping-pong¡± front-end block, designers can convert two data streams in the same ADC (in series, each sampled at half the ADC rate) effectively to halve the area use. Figure 3 illustrates the area gains between two DesignWare 12-bit dual ADCs for IQ data conversion implementations that use the same high-speed ADC core, one implementing two parallel ADCs and the other making use of the optional ping-pong front-end.
Figure 3: Comparison of two 40-nm DesignWare 12-bit dual ADC IP for IQ data conversion implementations using the same high-speed ADC core and the optional ping-pong front-end: total area reduction is ~40%
3. Power consumption reduction
Power consumption is another critical aspect of analog interfaces, in particular for battery powered applications. To reduce power consumption, Synopsys analyzed real-life ADC use cases inside the complete system to derive the most efficient architecture for the ADC itself 2 . By applying suitable circuit design techniques, the power dissipation of the ADC could be reduced to the minimum, as is demonstrated by the silicon measurements of the DesignWare 12-bit 250 MSPS ADC IP shown in Figure 4.
Figure 4: Low current consumption and small variation across supply voltage range (3 samples)
DesignWare Data Converter IP
The DesignWare ADC architecture offers multiple configurations to give customers design flexibility. For example, it comprises 10-bit and 12-bit solutions, dual (IQ) and single channel configurations, and the area-saving ping-pong configuration. Furthermore, several front-end stages are available and can be added to the ADC IP to create configurations for specific system conditions (e.g., input isolation buffer, dedicated Sample&Hold with embedded level shifter for large common mode range support, and support for different I/O supply levels).
Synopsys has silicon-validated ADCs that incorporate this advanced architecture in TSMC65LP, TSMC40LP and SMIC40LL. Other blocks that make up the analog interface, such as the transmit IQ-digital-to-analog converter (DAC) 2 , the auxiliary ADC and DAC, and a phase-locked-loop (PLL), are available in the same process nodes.
Sources:
1 Pedro Figueiredo, ¡°Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP¡± white paper, Synopsys, August 2012
2 Manuel Mota, article, ChipEstimate Tech Talk, July 2012