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Keeping Latency to a Minimum with 400G/800G Ethernet IP
A large volume of data is required for high performance computing (HPC) workloads in data centers. As a result, enabling data processing between machines and servers across long reach channels at high rates becomes mandatory. SoCs for HPC applications such as data center, networking and AI, must support high throughput and minimum latency with maximum channel insertion loss. Designers can meet such requirements with compliant IP on most advanced FinFET processes.
Attend this Synopsys webinar to learn how to:
- Meet the performance and power targets of your HPC SoCs requiring 100G, 200G, 400G 800G Ethernet links
- Minimize latency across long reach channels with an integrated Ethernet MAC and SerDes PHY IP solution that includes PCS, PMD, PMA and auto negotiation functionalities
- Get ready for the world of 1.6Tb Ethernet and its required building block
Speakers
John Swanson
Sr. Product Marketing Manager
Synopsys
John Swanson is the Sr. Product Marketing Manager for a portfolio of high-performance computing IP including Ethernet, PCI Express, CXL and CCIX as well as the mathematical and datapath IP. He has been working on System-on-a-Chip technologies and methodologies for over 25 years with Synopsys in a variety of assignments. John has worked in the design, verification, integration, and implementation aspects of complex IP in engineering methodology, and business development and marketing. He is an Honor graduate from DeVry Institute of Technology where he completed his engineering degree with Presidents List honors.
Priyank Shukla
Staff Product Marketing Manager
Synopsys
Priyank Shukla is a Staff Product Marketing Manager for the Synopsys High Speed Serdes IP portfolio. He has broad experience in analog, mixed-signal design with strong focus on high performance compute, mobile and automotive SoCs. Priyank has a US patent on low power RTC design. He received an Electrical Engineering degree from the Indian Institute of Technology-Madras.
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