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In today¡¯s landscape of generative AI, IoT, and more, the demand for advanced RISC-V core IP is rapidly escalating. As technology becomes increasingly software-driven, the industry has shifted from developing hardware first and software second to a new paradigm where applications, particularly large language models in AI, are driving the architectural development. This shift has positioned RISC-V at the forefront due to its highly configurable instruction set architecture (ISA).

This flexibility is crucial as it allows developers to tailor the instruction set to specific software needs, optimizing execution, power consumption, and throughput. A robust ecosystem of semiconductor companies, including Synopsys and SiFive, is developing RISC-V IP cores to meet the increased demand. This ecosystem offers a range of products that enable customers to create their own RISC-V implementations, customizing the instruction set to achieve optimal performance for their specific applications. The ability to fine-tune and adapt RISC-V cores provides significant advantages in various market segments.

While AI is a major driver for RISC-V adoption, its applications extend to include general purpose processors for many different kinds of products all the way to 64-bit processors. The general-purpose processor market is highly competitive, with RISC-V IP providers going head-to-head with established players. This competition drives innovation and offers customers more choices in processor IPs, ultimately benefiting the industry as a whole.

Enter SiFive¡¯s broad portfolio of RISC-V core IPs, from simple embedded microcontrollers all the way to high-end 64-bit application processor cores. Read on to learn more about SiFive¡¯s portfolio, Synopsys¡¯ HAPs prototypes, and how together they are enabling one trillion verification cycles per day. 

SiFive¡¯s Advanced RISC-V Processor Portfolio

Speed is the name of the game in terms of both development and verification. That¡¯s why SiFive devised an innovative development environment to rapidly craft CPUs tailored to customers¡¯ specific needs. Equally critical, they also develop companion compilers for each CPU they produce. However, one significant challenge of this large and diverse portfolio is verification and software validation.

¡°SiFive¡¯s unique design methodology has enabled us to build the world¡¯s leading RISC-V portfolio with a broad range of products and options for our customers,¡± said Rajesh Ramalingam Varadharajan, engineering manager at SiFive. ¡°Customers demand the highest quality standards, so verification and validation play a critical role in ensuring production ready products. We use FPGA prototypes for various verification tasks, encompassing functional verification, regression testing, and comprehensive validation of the entire software stack. Each of our RISC-V IPs undergoes extensively testing using real-world software workloads executed under the Linux OS.¡±

To solve the need for lightning-fast verification, SiFive utilizes Synopsys¡¯ HAPS prototyping systems which employ four FPGAs. These can be utilized independently in configurations of one, two, or four FPGAs. For example, smaller RISC-V IPs may fit within one or two FPGA, while larger ones need all four. 

Today, SiFive uses tens of units of HAPS-100, each housing four FPGAs. Each FPGA can execute roughly 864 billion cycles per day, meaning SiFive¡¯s throughput is trillions of cycles every day. This is important because they support many configurations to satisfy all of their customers' various RISC-V designs.

The Future of RISC-V Core IP

The need for advanced RISC-V core IP and fast chip verification solutions has been driven by the evolving requirements of modern software applications, particularly in AI. The flexibility and configurability of RISC-V make it an ideal choice for optimizing performance across a variety of applications. 

IP verification and software validation for a large and diverse portfolio of cores can be addressed with a scalable prototyping platform. Synopsys¡¯ FPGA-based HAPS platforms have proven to be successful for SiFive due to being the fastest on the market which also translates into trillions of verification cycles, ultimately driving a high return on investment. Forthcoming new RISC-V core generations will be larger and more complex than the previous ones, driving the need for more prototyping due to the corresponding larger number of bugs that could pop up and test cycles needed to combat those. SiFive will address this complexity by connecting multiple HAPS platforms together to address the need for running validation cycles on more complex RISC-V cores. 

With a strong ecosystem of IP providers and a competitive market landscape, RISC-V is poised to continue its growth and drive innovation in the technology sector. Stay tuned for more updates on how Synopsys and our customers like SiFive are pushing the boundaries of what¡¯s possible with RISC-V technology.