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The fact that the battery for your multi-tasking, feature-rich smartphone can run as long as it does between charges is a testament to the delicate power management tradeoffs that mobile device designers must perform. Chips running in today¡¯s phones commonly have billions of gates, upwards of 20 million lines of code, and hundreds of power domains. Keeping the device at optimal, energy-efficient performance levels requires the right balance.
For years now, chip designers have designed their SoCs so that certain parts go into sleep mode when they aren¡¯t needed. For example, if you¡¯re using a mapping application on your smartphone, the part of the chip responsible for running your email system can be shut off. Ensuring that the chip is ready for prime time, however, can be a daunting task.
Considering the size and complexity of today¡¯s low-power SoCs, verification and signoff are growing increasingly challenging. Yet, these steps are more critical than ever, as undetected bugs could prove detrimental or even fatal to the chip. Fortunately, SoC verification technologies have evolved to support today¡¯s massive chip designs. For example, Synopsys VC LP? static low power verification solution provides more than 650 checks with full-chip capacity and performance for complete low-power static signoff. And now, the solution has been enhanced with advanced functional checks that allow verification engineers to catch potential functional issues that would otherwise be very resource-intensive to detect during simulation. Read on to learn more about how the Synopsys VC LP solution facilitates faster, more comprehensive debug to help you deliver high-quality, high-performing silicon.
Faster SoC Debug Through Machine Learning and Hierarchical Approach
From mobile devices to servers and networking equipment, more of today¡¯s electronic products require advanced power management. Low-power SoC design techniques such as power gating, retention, low-VDD standby, use of isolation cells, and dynamic voltage scaling (DVS) enable fine-grained power management, using the industry-standard IEEE 1801 Unified Power Format (UPF) power intent language as the common language to specify the design¡¯s power intent. However, these techniques also add new design elements at different stages of the design flow. The nature of low-power SoC design architectures and behavior makes chip verification and signoff much more challenging than for always-on SoC designs.
This is where a static checking solution like VC LP technology can enhance and accelerate the debug process and allow the simulation process to focus on catching dynamic low-power bugs. The Synopsys VC LP solution can be run at RTL, post-synthesis, and post place and route to catch low-power bugs earlier and faster than traditional methods. It also provides the valuable ability to operate low-power static checking comprehensively in all stages of the design flow for accurate verification of the design¡¯s correct implementation and behavior.
While such static checking tools traditionally have been run on small blocks, perhaps at the IP level, the capacity of the VC LP solution has expanded to run on larger blocks, bigger designs, and even the full chip. Multi-threading solves any runtime issues, while the solution¡¯s machine learning- (ML-) driven engine points engineers to the location of problems and their root causes and effects. Let¡¯s take a closer look at two of the newest capabilities.
ML-Driven Root-Cause Analysis
Some of today¡¯s large designs may have as many as one million violations, so a solution with the intelligence to categorize the problems and provide clues on how to solve them can save substantial time and effort. Engineers can then focus on analysis and resolving the causes of the violations. Realistically, managing large report volumes for signoff through manual debug is not very feasible and can be error prone.
Figure 1: Synopsys VC LP ML-driven root-cause analysis results.
The ML-driven root-cause analysis capability in the Synopsys VC LP solution reduces debug time by creating ¡°smart groups¡± and pointing out the exact root cause to the user. Users can categorize existing violations into smart clusters, capturing violation causes and violation effects. This allows the user to focus on analyzing and fixing the violation causes.
Static Abstraction Models
Static Abstraction Models (SAM) in the VC LP solution enable hierarchical verification with optimal quality of results (QoR) and, compared to flat runs, better performance. The models contain only the part of the block-level logic that interacts with the top level or other blocks; any crossovers which are completely contained inside the block are dropped. Top-level integrators can then focus on top-level violations and integrations, without having to worry about violations deep inside hierarchies that block owners would ordinarily address. Customers have achieved up to 15x capacity and runtime gains using the SAM flow, along with reduced memory usage.
Figure 2: Synopsys VC LP static abstraction model hierarchy.
Summary
From smartphones to servers, power-sensitive devices and systems demand low-power SoCs that deliver the performance expected with the energy efficiency needed. While advanced power management techniques deliver the desired outcomes, they also contribute to the verification and signoff challenges for low-power designs.
With its newest enhancements, the Synopsys VC LP static low-power verification solution helps engineers find and fix power-related bugs earlier in the cycle. Given the size and complexity of today¡¯s low-power SoCs, having a debug aid with ML-driven smarts and massive capacity can make your life easier and the products you develop that much better.