Cloud native EDA tools & pre-optimized hardware platforms
Safety features have always been important in the automotive industry; it has certainly become the most critical requirement for autonomous vehicles. Have you ever wondered what technology makes it possible for multiple sensors located at front, rear sections and inside the doors to work in a coordinated manner for early crash detection and operate the vehicles air bags thereby protecting precious human life?
The Motorola SPI (Serial Peripheral Interface) and its variants have been a popular choice among system designers thanks to low pin count and compact design features. With growing safety requirements, an industry standard interface is required now, more than ever, to avoid multiple vendor interfaces with custom drivers. SafeSPI industry standard is designed to support the time sensitive requirements of active and passive safety systems alongside qualities of SPI.
Automotive systems, particularly safety systems, require an ASIC transceiver communicating with sensors and a safety controller in one package and reliable communication between the ASIC and control unit. The optimal ¡®signal quality at control unit¡¯ allows it to swiftly respond to critical scenarios per the ASIL (Automotive Safety Integrity Level) Ready ISO 26262 safety specifications.
In the automotive industry SafeSPI based MEMS (Micro Electro Mechanical Systems) components are deployed for active and passive safety systems as well as driver assistance systems. The reliability of SafeSPI is critical to the success of MEMS based automotive devices. Next generation automobiles make driving easier and safer with features like RSC (roll over stability control), AD (active damping) systems, and RoSe (rollover sensing) by combining on chip self-monitoring and a controller in one unit with the SafeSPI interface. SafeSPI supports in-frame and out-frame configurations with following features:
Synopsys VC VIP is the industry¡¯s first VIP for SafeSPI. Synopsys VIP, based on next-generation native System Verilog and UVM architecture, provides built in verification plans and coverage for accelerated verification closure. The VIP provides coverage-driven exhaustive directed and random sequences, and runtime configurable options to select between multiple modes that cater to a wide range of industry requirements. VIP also supports integrated Verdi? Protocol Analyzer for advanced debug capabilities.